Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization

ABSTRACT

This process consists of producing patterns (17) of an insulating material on a monocrystalline silicon substrate (12), depositing on the complete structure an amorphous or polycrystalline silicon film (26), covering the latter with a layer (28) of an encapsulating material, carrying out a heat treatment on the structure obtained serving to vertically embed in substrate (12) the insulating material patterns (17) and forming above the latter a monocrystalline silicon layer (33), eliminating the encapsulating material layer (28) and etching the monocrystalline silicon layer obtained (33), so as to form said islands (34).

The present invention relates to a process for the production ofmutually electrically insulated monocrystalline silicon islands. It moreparticularly applies to the field of producing bipolar or MOS integratedcircuits of the silicon on insulant type, in which components operatingunder "high voltage" must be electrically insulated from componentsoperating under "low voltage".

The silicon on insulant technology used for producing mutually insulatedmonocrystalline silicon islands constitutes a significant improvementcompared with the standard methods in which the active components ofintegrated circuits are directly produced on a solid siliconmonocrystalline substrate. Thus, the use of an insulating material leadsto a considerable decrease in the stray capacitances between the sourceand the substrate on the one hand and the drain and the substrate on theother of the active components of the integrated circuit andconsequently to an increase in the operating speed of said circuit. Italso leads to a significant simplification in the production processes,an increase in the integration density and a better behaviour of thecircuit to high voltages.

One of the presently known methods for producing a monocrystallinesilicon layer on an insulating support is diagrammatically shown inlongitudinal sectional form in FIG. 1. This technology consists offorming on a type n or p monocrystalline silicon substrate 2, siliconoxide patterns 4 and then forming by gaseous phase deposition a thickpolycrystalline silicon layer 6 surmounting said oxide patterns. On thecomplete polycrystalline silicon layer 6 is then deposited an insulatingsilicon oxide layer 8, more particularly by a chemical gaseous phasedeposition process (LPCVD).

The following stage consists of recrystallizing the polycrystallinesilicon layer 6 in monocrystalline form. This recrystallization consistsof melting the silicon of layer 6 by heating it through the oxide layer8 by means of a heating source. On cooling, the silicon layer 6recrystallizes in monocrystalline form from the substrate 2, which thenacts as a germ for growth. Mutually insulated monocrystalline siliconislands can then be produced in this monocrystalline silicon layer.

This process for obtaining a monocrystalline silicon layer on an oxidelayer has in particular been described in an article in Materialsresearch society symposia proceedings, vol 13, 1983 entitled "Lateralepitaxial growth of thick polysilicon films on oxidized three inchwafers" by G. K. Celler et al, pp 575 to 580.

This process suffers from a certain number of disadvantages. Inparticular, the surface of the recrystallized silicon layer 6 has anoften significant roughness and the surface of the recrystallized zoneson the oxide patterns 4 is not planar. These surface states impose asupplementary stage of polishing the surface of the recrystallized layer6. Moreover, this process has a only a limited efficiency. Thus, theratio of the zones recrystallized on insulant to the unused zones persilicon wafer is approximately 50%. Moreover, this process uses anepitaxy deposit of the silicon layer to be recrystallized, whichgenerally takes a long time and is difficult to carry out. Finally, thealignment of the future resin masks for producing the components abovethe insulating patterns 4 is difficult to obtain by photolithography,because the recrystallized silicon of layer 6 is no longer transparentin the irradiation range generally used for the alignment of the masks.

The present invention relates to a process for the production ofmutually electrically insulated monocrystalline silicon islands makingit possible, inter alia, to obviate the aforementioned disadvantages.

According to the invention, the production process comprises thefollowing successive stages:

(a) producing patterns of a first insulating material on amonocrystalline silicon substrate,

(b) depositing a thin silicon film on the complete structure,

(c) covering the silicon film with a layer of an encapsulating material,

(d) carrying out a heat treatment on the structure obtained forvertically embedding in the substrate the patterns of the firstinsulating material and for forming above said embedded or buriedpatterns a monocrystalline silicon layer,

(e) eliminating the encapsulating material layer and

(f) etching the monocrystalline silicon layer obtained so as to formsaid islands.

The silicon film can be a polycrystalline silicon film or an amorphoussilicon film.

The process of the invention more particularly makes it possible toobtain mutually insulated monocrystalline silicon islands, which arefree from any crystalline defects. Moreover, the surface of themonocrystalline silicon layer obtained is smooth and planar and inparticular above the insulating patterns, which makes it possibleobviate, compared with the prior art, a supplementary stage of polishingthe surface of said monocrystalline layer. This advantage is increasedin the variant of the invention in which the thin silicon film depositedis a thin amorphous silicon film, because such a film has an excellentsurface state (smooth surface).

Furthermore, the wafer efficiency of this process is higher than in theprior art, the ratio of recrystallized on insulant zones to the unusedzones being close to 80%. Preferably, the patterns of the firstinsulating material are in the form of continuous parallel strips, whichare regularly spaced from one another.

Advantageously the heat treatment consists of on the one hand heatingthe face of the silicon substrate opposite to the silicon film in auniform manner to a temperature below the silicon melting temperatureand on the other hand the silicon film by means of an elongated heatingsource, the heating of the film being carried out by performing arelative sweep between the heating source and the film thesesimultaneous heating operations of the film and the substrate facebringing about a melted silicon zone moving over the entire surface ofthe film and the substrate.

In the case of first insulating material patterns in the form ofparallel strips, the relative sweep between the source and the siliconfilm takes place in a direction parallel to said strips. This makes itpossible to prevent any minor lateral displacements of the firstinsulating material patterns, when the latter are embedded in themonocrystalline substrate.

According to a first embodiment of the process according to theinvention, stage (f) is performed in the following way:

producing a mask on the silicon layer obtained having the image of thefirst insulating material patterns, elimination of the unmasked siliconlayer regions up to the level of the first insulating material patternsembedded in the substrate and elimination of the mask.

According to another procedure for performing the inventive process,following stage (f), the edges or flanks of the islands and regions ofthe substrate exposed between said islands are covered with a layer of asecond insulating material.

Advantageously, following stage (f), the spaces between the islands arefilled by a third material, which is preferably a polyimide resin.

Other features and advantages of the invention can be gathered from thefollowing description given in an illustrative and non-limitative mannerwith reference to the attached drawings, wherein show:

FIG. 1, already described, diagrammatically and in longitudinal sectionillustrates the different stages of a process for producing amonocrystalline silicon layer according to the prior art, in whichsilicon islands can be produced.

FIGS. 2, 3, 8 to 14, diagrammatically and in longitudinal section thedifferent stages of the process according to the invention.

FIGS. 4 to 6, diagrammatically a variant of this process.

FIG. 7, diagrammatically an apparatus making it possible to perform theprocess according to the invention.

The first stages of the process consist of producing insulating materialpatterns (FIGS. 3 and 6) on a monocrystalline silicon substrate.

For this purpose and according to a first variant shown in FIG. 2, atype n or p monocrystalline silicon substrate 12, e.g. constituted by asilicon wafer cut along crystallographic plane 100, is covered with alayer 14 of a first insulating material, preferably constituted bysilicon oxide. This insulating layer 12 can be obtained by thermaloxidation of substrate 12, under dry or wet oxygen at a temperature ofapproximately 800° to 1100° C., or deposited on the substrate by achemical gaseous phase deposition process (pyrolysis at approximately420° C. of SiH₄ and O₂). This oxide layer 14 e.g. has a thickness ofapproximately 1 μm.

A resin mask 16 is then produced on the silicon oxide layer 14 byconventional photolithograpy processes in order to define the dimensionsof the oxide patterns to be produced in layer 14. In the manner shown inFIG. 3, this is followed by etching of the oxide layer 14, so as toexpose the regions of the substrate not covered by mask 16. This etchingcan be carried anisotropically using a plasma etching process, orisotropically, e.g. by a chemical procedure using hydrofluoric acid asthe etching agent. The structure shown in FIG. 3 results from achemical-type etching.

This is followed by the elimination of mask 16, more particularlychemically or by etching an oxygen plasma. The insulating patternobtained in this way on substrate 12 carry reference 17.

FIGS. 4 to 6 show another variant of the patterns in insulating materialon substrate 12. As shown in FIG. 4, there is firstly a thermaloxydation of substrate 12, under oxygen and at a temperature ofapproximately 1000° C., so as to obtain a silicon oxide layer 18. Oxidelayer 18 has a thickness of approximately 60 nm.

On said oxide layer 18 is then deposited an insulating layer 20, moreparticularly of silicon nitride, using a low pressure chemical vapourphase deposition process (pyrolysis of NH₃ +SiH₂ CL₂ at 800° C.). Thislayer has a thickness of approximately 80 nm. This layer willsubsequently serve as a mask for defining the dimensions of theinsulating material patterns placed over the substrate.

On the nitride layer 20 is then formed a resin mask 22, which iscomplementary to mask 16 (FIG. 2) making it possible to define withinthe nitride layer 20 complementary patterns 2a (FIG. 5) with respect tothose to be obtained on substrate 12. This is followed by theelimination of the regions of the nitride layer 20 which are not masked,so as to expose the underlying regions of the silicon oxide layer 18.This elimination can be carried out by an antisotropic or isotropicetching process and in particular by chemical etching usingorthophosphoric acid as the etching agent, or by fluorine plasmaetching.

With the aid of the etched nitride layer 20 and optionally mask 22, inthe same way the oxide layer 18 is then etched until the substrateregions not covered by the etched layer 20 are exposed. The patternsproduced in the oxide layer 18 carry the reference 18a (FIG. 5). Thisetching operation can be performed anisotropically or isotropically,e.g. by chemical etching using hydrofluoric acid as the etching agent.The structure obtained is shown in FIG. 5. The resin mask 22 can beeliminated chemically, using acetone as the etching agent.

The following stage of the process consists of thermally oxidizing theexposed substrate zones under dry or wet oxygen at a temperature between800° and 1100° C. This thermal oxidation makes it possible to obtainoxide patterns 24, which are partly buried in substrate 12. This isfollowed by elimination, e.g. chemically using orthophosphoric acid ofthe remainder 20a of the nitride layer, followed by the elimination ofthe remainder 18a of the oxide layer, e.g. chemically using hydrofluoricacid. The structure obtained is shown in FIG. 6. This technology isgenerally known under the name LOCOS technology.

It is also possible according to the present invention to produceinsulating patterns 24 which are completely buried in substrate 12 andfollowing the etching of oxide layer 18 and silicon nitride layer 20(FIG. 5), it is then merely necessary to etch over a certain height(close to 300 nm) the substrate regions not covered by the remainder18a, 20a of the corresponding layers. This etching can be carried outisotropically and particularly chemically using a potassium solution.

Advantageously, the oxide patterns 17 or 24, respectively produced onsubstrate 12 or buried therein, preferably have in the manner shown inFIG. 7 showing a plan view of the structure of FIG. 3, the form ofcontinuous parallel strips, which are regularly spaced from one anotherand extend from one end to the other of substrate 12, or in other wordsthe silicon wafer. These insulating strips 17 are uniformly distributedover the entire surface of substrate 12. For example, for a 100 mm²silicon wafer, it is possible to produce 10 to 20 μm wide insulatingstrips 17 with a reciprocal spacing of 4 μm.

The following stages of the process obviously relate to the insulatingpatterns 17 or 24 obtained on or in the substrate according to theprevious above-described variants. However, in order to facilitate thefollowing description, this will relate to the insulating patterns 17obtained in an insulating layer by the etching thereof in accordancewith the first variant described relative to FIGS. 2 and 3.

As shown in FIG. 8, on the complete structure is deposited apolycrystalline or amorphous silicon film 26, e.g. having a thickness ofapproximately 0.5 μm. The polycrystalline silicon film can be obtainedby a low pressure chemical vapour phase deposition process at atemperature of approximately 600° C. by pyrolysis of SiH₄. In the sameway, the amorphous silicon film can be obtained by low pressure, lowtemperature (below 550° C.) vapour phase deposition. Film 26 is thencovered with an encapsulating layer 28, e.g. of silicon oxide, orsilicon nitride, or even in multilayer form, a silicon oxide layer and asilicon nitride layer. Encapsulating 28 e.g. has a thickness of 1.5 to 2μm and can be obtained by a low pressure chemical vapour phasedeposition process at 430° C. by pyrolysis of SiH₄ +O₂, when said layeris of silicon oxide.

The following stage of the process consists of subjecting the structureobtained to heat treatment, which makes it possible to recrystallize thesilicon layer 26 in monocrystalline form, as well as vertically embed insubstrate 12 the oxide patterns 17. The structure obtained is shown inFIG. 9.

This heat treatment consists of heating substrate 12 from the rear, asshown by arrow F₁, i.e. face 12a of said substrate opposite to thesilicon film 26. Substrate 12 is heated uniformly at a relatively hightemperature, but which is below the melting temperature of themonocrystalline silicon constituting the substrate, i.e. a temperatureof approximately 1300° C. This can e.g. be brought about by placing thesubstrate 12 on a graphite heating plate carrying reference 30 in FIG.7.

Simultaneously with the heating of substrate 12, the silicon film 26 isheated through the encapsulating layer 28 using an elongated heatingsource 32, e.g. formed by a heated graphite bar (FIG. 7) or a focusedlinear lamp, or some other focused, linear energy beam. This heating offilm 26 is carried out by effecting a relative sweep between source 32and the sample and consequently film 26, e.g. by keeping the sample i.e.the film fixed and by moving source 32 over the entire sample surface,as indicated by arrows F₂.

It should be noted that substrate 12 can also be heated by using a setof linear lamps positioned parallel to the upper linear source 32.

These simultaneous heating operations of substrate 12 and silicon film26 make it possible to bring about a molten silicon surface zone movingover the entire surface of the film and the substrate. Preferably and asshown in FIG. 7, source 32 is moved parallel to the insulating patterns17, when the latter have the advantageous form of parallel continuousstrips.

The depth to which the insulating patterns 17 can be embedded or buriedcan be accurately adjusted by acting on the sweep rate of source 32 andon the width of the moving molten surface zone, said width correspondingto the width corresponding to the width of source 32. For example a 5 mmwide source and with a displacement speed of 0.2 mm/s enables insulatingpatterns 17 to be buried to a depth of 20 μm in the substrate.

Such a heating apparatus has more particularly been described in thearticle In Journal of crystal growth, (63) 1983 entitled "Graphitestrip-heater zone-melting recrystallization of Si films" by J. C. C. Fanet al.

Another heating apparatus usable in the invention is that described inFrench patent application 2532783 filed on Sept. 7, 1982 and which useslinear lamps focused on the side of the film.

The fact that the insulating patterns are buried vertically in thesubstrate, without any lateral displacement with respect to theirinitial position, makes it possible to localize then with respect to thesurface of the sample which retains the initial relief and consequentlymakes it possible to bring about the alignment of the subsequent stagesnecessary for the production of the monocrystalline islands. Thisalignment is facilitated when the insulating patterns are obtained bythe so-called LOCOS or buried LOCOS technology (FIG. 6).

The previously melted silicon above the buried insulating patterns 17recrystallizes on cooling. It is free from any crystalline defect andhas an absolutely planar and smooth surface. The monocrystalline siliconlayer obtained surmounting the insulating patterns carries the reference33.

As shown in FIG. 10, the following stage of the process consists ofeliminating the encapsulating layer 28, e.g. chemically in ahydrofluoric acid bath when said layer 28 is made from silicon oxide, orin an orthophosphoric acid bath, in the case of a silicon nitride layer.

The following stages of the process consist of etching themonocrystalline silicon layer 33 obtained above the oxide patterns 17 toform within said layer mutually insulated monocrystalline siliconislands.

As shown in FIG. 10, on the monocrystalline silicon layer 33 is firstlydeposited a layer 30 of a material which is not sensitive to the etchingagents for layer 33. This deposition can be carried out by a chemicalvapour phase deposition process. As layer 30 has a thickness ofapproximately 100 nm, it can be formed from silicon oxide or siliconnitride.

Using conventional photolithography processes, on insulating layer 30 isthen placed a resin mask 31 representing the image of the insulatingpatterns 33 embedded in the monocrystalline silicon and making itpossible to mask said patterns. The fact that the monocrystallinesilicon layer 33 has a relief corresponding to the relief prior to theembedding of the insulating patterns 17 makes it possible to correctlyposition the resin mask 32.

In the manner shown in FIG. 11, insulating layer 30 is then etched so asto eliminate the unmasked regions of layer 30 until monocrystallinelayer 33 is exposed. This etching can be carried out isotropicallyadopting a chemical procedure, respectively using as the etching agenthydrofluoric or orthophosphoric acid for a silicon oxide or siliconnitride layer 30, or anisotropically using an oxygen plasma.

Following the elimination of the resin mask 31, more particularlychemically using acetone or nitric acid as the etching agent, in themanner shown in FIG. 12 the regions of the monocrystalline layer 33 freefrom the remainder of protective layer 30 are eliminated. Thiselimination can be carried out isotropically e.g. using a chemicaletching process with a potassium solution as the etching agent. Thisetching is carried out up to the level of the insulating patterns 17,the flanks of said patterns being exposed. It makes it possible toobtain monocrystalline silicon islands 34, which are clearly separatedfrom one another.

Following the etching of monocrystalline layer 33 and consequently theproduction of islands 34, the remainder of insulating layer 30 used asthe mask for said etching operation can be eliminated, e.g. chemicallyusing hydrofluoric acid in the case of a layer 30 made from siliconoxide or using orthophosphoric acid in the case of a layer 30 made fromsilicon nitride.

The following stage of the process consists of electrically andeffectively insulating the monocrystalline islands 34 from one another.This insulation can be obtained by covering the structure obtained withan insulating layer 30, which can more particularly be of silicon oxide.This insulating layer 36 with a thickness of several hundred nanometerscan be obtained by thermal oxidation under oxygen of the exposed regionsof substrate 12, as well as the monocrystalline islands 34.

Oxide layer 36 can then be etched so as to only retain those portions ofsaid layer located on the flanks of the monocrystalline islands 34 andon those regions of substrate 12 located between two contiguous islands.The structure resulting from this etching is shown in FIG. 13. Ashereinbefore, the elimination of certain portions of the insulatinglayer 36 can be carried out by using a not shown mask covering thesurface of the monocrystalline islands 34 and using an isotropic oranisotropic etching process, such as chemical etching with hydrofluoricacid.

In conventional manner, it is possible to then produce in theelectrically mutually insulated monocrystalline islands 34, the activecomponents of an integrated circuit and in particular the componentsoperating under high voltage, such as bipolar or DMOS transistors,insulated from the components operating under low voltage, such asbipolar, CMOS or N-MOS transistors.

FIG. 13 shows a DMOS transistor 38 produced on a first monocrystallineisland, which is provided in a conventional manner with a source 40 anda drain 42, diffused in said island, as well as a gate 44 insulated fromthe source and drain, as well as a CMOS inverter 46 produced on a secondmonocrystalline island formed from a N-channel transistor 48 and a Pchannel transistor 50, which are insulated from one another by a fieldoxide 52 obtained in the conventional way. In per se known manner,transistor 48 comprises a source 54, a drain 56 and a gate 58 insulatedfrom the source and drain, whilst transistor 50 has a source 60, a drain62 and a gate 64.

The different components produced in the monocrystalline silicon islands34, such as CMOS inverter 46 and DMOS transistor 38 are produced in aconventional manner up to the metallization stage used for bringingabout the interconnections of these components. Thus, prior toperforming said metallization, the holes or spaces 66 between thedifferent monocrystalline islands 34 are filled. As shown in FIG. 14,this filling can be carried out with a polyimide resin 68, which isdeposited on the complete structure using a whirling means, followed byetching so as to eliminate those portions of said resin outside thespaces or holes 66. This elimination can be carried out by a reactiveionic etching process using a so-called planarization method.

The interconnections of the different components of the integratedcircuit and in particular connection 70 between the low voltage CMOScomponent 46 and the high voltage DMOS component 38 can then be producedin a conventional manner. These interconnections are obtained bydepositing on the complete structure a conductive layer, particularly ofaluminium, with a thickness of 1 μm, followed by the etching of saidlayer so as to produce the different connections.

Obviously the above description has only been given in an illustrativemanner. In particular, all modifications can be made with regards to thematerial of the material layers, their thickness, their deposition andetching processes.

We claim:
 1. A process for producing mutually electrically insulatedmonocrystalline silicon islands, comprising in succession:(a) producingcontinuous parallel strips of a first insulating material on amonocrystalline substrate, (b) depositing a non-monocrystalline siliconfilm on the insulated substrate, (c) covering said deposited siliconfilm with a continuous layer of an encapsulating material, (d)subjecting the obtained structure to a heat treatment, therebyvertically embedding said parallel strips in the substrate and formingabove said embedded strips a monocrystalline silicon film through saidencapsulating layer by a heating means, whereby said heating is effectedby sweeping said heating means in a direction parallel to said parallelstrips, and said heating forming a molten silicon zone moving across theentire surface of the film, whereby said continuous parallel stripsbecome embedded to the lower edge of said molten zone, said molten zoneconsisting essentially of said non-monocrystalline silicon layer and aportion of said substrate layer, (e) eliminating said encapsulatingmaterial layers, and (f) etching said monocrystalline silicon layerobtained, thereby forming said islands.
 2. The process according toclaim 1, wherein the non-monocrystalline silicon film is an amorphoussilicon film.
 3. The process according to claim 1, wherein thenon-monocrystalline silicon film is a polycrystalline silicon film. 4.The process according to claim 1, wherein the continuous parallel stripsare regularly spaced from one another.
 5. The process according to claim1, wherein the strips of the first insulating material are produced bycovering the substrate with a layer of said first insulating materialand then etching said layer until certain zones of said substrate areexposed.
 6. The process according to claim 1, wherein the firstinsulating material strips are obtained by performing the followingsteps:(a) covering the substrate with at least one preliminary layer ofinsulating material, (b) etching said preliminary layer so as to producein said layer patterns which are complementary to those to be obtained,and until certain substrate zones are exposed, (c) thermally oxidizingthe exposed zones of said substrate, and (d) eliminating the remainderof the preliminary layer.
 7. The process according to claim 6, whereinfollowing step (b), the exposed substrate zones are partially etched. 8.The process according to claim 1, wherein the first insulating materialis silicon oxide.
 9. The process according to claim 1, wherein theencapsulating material layer is formed from a silicon oxide layer or asilicon nitride layer or a combination thereof.
 10. The processaccording to claim 1, wherein the heat treatment comprises heating theface of the silicon substrate opposite to the silicon film in asubstantially uniform manner and at a temperature below the siliconmelting temperature.
 11. The process according to claim 1, wherein step(f) comprises:(a) producing a mask on the silicon layer obtained, whichrepresents an image of the strips of said first insulating material, (b)eliminating the regions of the silicon layer which have not been maskedup to the level of the strips of the first insulating material embeddedin said substrate, and (c) eliminating said mask.
 12. The processaccording to claim 11, wherein the mask is made from silicon oxide orsilicon nitride or a combination thereof.
 13. The process according toclaim 1, wherein after step (f), the flanks of the islands and thesubstrate regions exposed between said islands are covered with a layerof a second insulating material.
 14. The process according to claim 1,which further comprises following step (f), filling spaces between saidislands with a third material.
 15. The process according to claim 14,wherein the filling of the spaces is carried out by depositing on thecomplete structure a layer of said third material and by eliminating thethird material located outside of said spaces.
 16. The process accordingto claim 14, wherein the third material is a polyimide resin.
 17. Theprocess according to claim 1, wherein the silicon film has a thicknessof approximately 0.5 micrometers.